ADC In An FPGA, Part 2

June 5, 2011

This blog post has been moved to my new blog at intentionallogic.com.  Click here for ADC In An FPGA, Part 2.





  1. […]  Part 2 of this series is up.  Read it here, when you’re done with Part 1, of […]

  2. I’m an embedded/real-time programmer just starting down the FPGA learning curve.

    I have a no-frills breakout board for a Xilinx Spartan 3E500K-4 PQ208, and for my first project I want to do something “interesting” that will require minimal external components or interfaces (beyond JTAG).

    A digital audio effects system (guitar, voice, etc.) is my choice. For output, I figure my DAC will use digital output pins and a resistor ladder. My search for an all-digital audio-rate ADC led me to your blog.

    The neat thing about doing an audio effects generator is that the clock rates are fairly low and ADC only has to be ‘good enough’. And it may be possible to implement some effects within the ADC itself.

    I particularly like how your blog posts discuss not only the basic theory, but also address optimizations and other implementation considerations.

    Do you have any HDL code you’d care to share?

  3. I am a graduate student working on implementing soft ADCs utilizing just this approach for an advanced digital course. I realize this article is a few years old now, but do you plan on posting part 3?

  4. Hi, I am very interested in making a Drum kit midi interface in a Lattice ICE40 based FPGA using this technique. Can you please send me any HDL code (prefer Verilog, but anything would be great).


  5. […]  Part 2 of this series is up.  Read it here, when you’re done with Part 1, of […]

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